Cache overview

So far, the RRV64 core is equipped with private L1 instruction & data cache and unified L2 cache, the coherent L1 data cache is in progress.

The overall design of our internal memory hierarchy is illustrated in following blockdiagram.

Single core

../../_images/internal_memory_blockdiagram4.png

Fig.1 Single cache system

Multi-core

../../_images/internal_memory_blockdiagram3.png

Fig.2 Multi-core cache system